The copending and commonly assigned patent application entitled xe2x80x9cMethods for Manufacturing Semiconductor Devices Having a Non-Volatile Memory Transistorxe2x80x9d, with Tomoyuki Furuhata and Atsushi Yamazaki listed as inventors, is hereby incorporated by reference in its entirety. The copending and commonly assigned patent application entitled xe2x80x9cNon-Volatile Semiconductor Memory Devicesxe2x80x9d, with Tomoyuki Furuhata and Atsushi Yamazaki listed as inventors, is hereby incorporated by reference in its entirety. Japanese patent application no. 11-177146, filed Jun. 23, 1999, is hereby incorporated by reference in its entirety.
The present invention relates to semiconductor devices having a non-volatile memory transistor with a split-gate structure and includes a semiconductor device comprising a plurality of field effect transistors having different operation voltages.
In recent years, a mixed-mounting of various circuits has been utilized in view of various demands such as a shortened chip-interface delay, a lowered cost per circuit board, a lowered cost in design and development of a circuit board and the like. A mixed-mounting technology for mounting memory and logic has become one of the important technologies. However, such a mixed-mounting technology presents problems that result in complex processes and higher costs for manufacturing ICs.
Certain embodiments relate to a semiconductor device comprising a memory region including a split-gate non-volatile memory transistor. The device also includes a first transistor region including a first voltage-type transistor that operates at a first voltage level, a second transistor region including a second voltage-type transistor that operates at a second voltage level, and a third transistor region including a third voltage-type transistor that operates at a third voltage level. The second voltage-type transistor includes a gate insulation layer formed from at least two insulation layers.
In one aspect of certain embodiments, the second voltage-type transistor described above includes a gate insulation layer that is formed in the same step in which a gate insulation layer of the first voltage-type transistor is formed.
In another aspect of certain embodiments, the third voltage-type transistor described above includes a gate insulation layer formed from at least three insulation layers. Additionally, the third voltage-type transistor may include an insulation layer that is formed in the same step in which the gate insulation layer of the first voltage-type transistor is formed.
In yet another aspect of certain embodiments, the non-volatile memory transistor described above may include a source, a drain, a gate insulation layer, a floating gate, an intermediate insulation layer adapted to function as a tunnel insulation layer, and a control gate. The intermediate insulation layer may be formed from at least three insulation layers, with the first and second outermost layers of the three insulation layers, respectively, contacting the floating gate and the control gate. The first and second outermost layers may also be composed of insulation layers that are formed by a thermal oxidation method.
Still other embodiments related to an embedded semiconductor device, the embedded semiconductor device a plurality of semiconductor devices selected from the group consisting of a flash-memory, an SRAM memory, a RISC, an analog circuit, and an interface circuit. The plurality of semiconductor devices are embedded in an SOG. At least one of the semiconductor devices comprises a structure including a memory region including a split-gate non-volatile memory transistor and three transistor regions. The first transistor region includes a first voltage-type transistor that operates at a first voltage level. The second transistor region includes a second voltage-type transistor that operates at a second voltage level that is greater than the first voltage level. The third transistor region includes a third voltage-type transistor that operates at a third voltage level that is greater than the second voltage level. The second voltage-type transistor includes a gate insulation layer formed from at least two insulation layers.